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Communication Dans Un Congrès Année : 2019

Evaluation of Variable Bit-Width Units in a RISC-V Processor for Approximate Computing

Résumé

Among various power reduction methods, variable bit-width arithmetic units have been proposed in approximate computing literature. In this paper, we add a variable bit-width memory unit in a RISC-V processor. Integrating both computation and memory units with variable bit-width leads to a power reduction: from 7% to 29% for Sobel filter application and from 13% to 24% for an application that computes the position of a robotic arm (forwardk2j). We also propose a global energy model for a RISC-V processor with variable bit-width units (for computation and memory). This model allows us to evaluate the impact of various parameters in both the software application (e.g., the amount of instructions that can be executed with a reduced bit-width) and the hardware architecture (e.g., impact of potential reduction for each unit).
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Dates et versions

hal-02152410 , version 1 (17-06-2019)

Identifiants

Citer

Geneviève Ndour, Tiago Trevisan Jost, Anca Molnos, Yves Durand, Arnaud Tisserand. Evaluation of Variable Bit-Width Units in a RISC-V Processor for Approximate Computing. CF'19: Proceedings of the 16th ACM International Conference on Computing Frontiers, Apr 2019, Alghero, Sardinia, Italy. ⟨10.1145/3310273.3323159⟩. ⟨hal-02152410⟩
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