Vertical termination filled with adequate dielectric for SiC devices in HVDC applications
Résumé
To fully achieve the performance which SiC power devices potentially have, it is necessary to reduce the electric field crowding effect taking place at the junction edges. So far, numerous techniques have been adapted to improve the breakdown voltage mainly under the planar technology, using for example, guard ring, field plate (FP), semi-insulating polycystalline (SIPOS), junction termination extension (JTE), 3D RESURF... However for high voltage devices, these techniques have the drawback of consuming large areas. Recently, thanks to the advancement in the Micro Electro Mechanical Systems (MEMS) process technology, the deep trench termination (DT2) technique becomes an appropriate choice for future high voltage power device. The edge termination design used for improving the breakdown voltage (VBR) and reducing drastically the chip area comparing to the above conventional structures. This concept has been already demonstrated in Si technology.
Domaines
Energie électriqueOrigine | Fichiers produits par l'(les) auteur(s) |
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