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Conference Papers Year : 2009

High-level system modeling for rapid HW/SW architecture exploration

Abstract

The increasing complexity of system-on-chip design especially the software part of those systems has stimulated much research work on design space exploration at the early stages of system development. In this paper we propose a new methodology for system modeling based on a specific UML profile. It defines a high design abstraction level for modeling and analyzing hardware resource sharing between system elements. Additionally, a SystemC-based simulator is developed in order to simulate modeled systems and evaluate their performance. Due to the high level of abstraction, the developed simulator enables fast exploration of design solutions. First promising results are presented and discussed over a mobile platform for the 3GPP LTE protocol stack.
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Dates and versions

hal-02124754 , version 1 (16-06-2022)

Licence

Attribution - NonCommercial

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Chafic Jaber, Andreas Kanstein, Ludovic Apvrille, Amer Baghdadi, Patricia Le Moënner, et al.. High-level system modeling for rapid HW/SW architecture exploration. IEEE/IFIP International Symposium on Rapid System Prototyping (RSP '09), Jun 2009, Paris, France. pp.88-94, ⟨10.1109/RSP.2009.27⟩. ⟨hal-02124754⟩
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