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Conference Papers Year : 2019

MixLock: Securing Mixed-Signal Circuits via Logic Locking


In this paper, we propose a hardware security methodology for mixed-signal Integrated Circuits (ICs). The proposed methodology can be used as a countermeasure for IC piracy, including counterfeiting and reverse engineering. It relies on logic locking of the digital section of the mixed-signal IC, such that unless the correct key is provided, the mixed-signal performance will be pushed outside of the acceptable specification range. We employ a state-of-the-art logic locking technique, called Stripped Functionality Logic Locking (SFLL). We show that strong security levels are achieved in both mixed-signal and digital domains. In addition, the proposed methodology presents several appealing properties. It is non-intrusive for the analog section, it incurs reasonable area and power overhead, it can be fully automated, and it is virtually applicable to a wide range of mixed-signal ICs. We demonstrate it on a Σ∆ Analog-to-Digital Converter (ADC).
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Dates and versions

hal-02094516 , version 1 (09-04-2019)


  • HAL Id : hal-02094516 , version 1


Julian Leonhard, Muhammad Yasin, Shadi Turk, Mohammed Thari Nabeel, Marie-Minerve Louërat, et al.. MixLock: Securing Mixed-Signal Circuits via Logic Locking. Design, Automation and Test in Europe (DATE 2019), Mar 2019, Florence, Italy. pp.84-89. ⟨hal-02094516⟩
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