LiteX [1] is a GitHub-hosted SoC builder / IP library and utilities that can be used to create SoCs and full FPGA designs. Besides being open-source and BSD licensed, its originality lies in the fact that its IP components are entirely described using Migen Python internal DSL, which simplifies its design in depth. LiteX already supports various softcores CPUs and essential peripherals, with no dependencies on proprietary IP blocks or generators. This paper provides an overview of LiteX: two real SoC designs on FPGA are presented. They both leverage the LiteX approach in terms of design entry, libraries and integration capabilities. The first one is based on RISC-V core, while the second is based on a LM32 core. In the second use case, we further demonstrate the use of a fully open-source toolchain coupled with LiteX.