Performance and Reliability of a Fully Integrated 3D Sequential Technology - Archive ouverte HAL
Communication Dans Un Congrès Année : 2018

Performance and Reliability of a Fully Integrated 3D Sequential Technology

Résumé

We investigate in detail, for the first time, both performance and reliability of a 3D sequential integration process. It is clearly demonstrated that the top level transistor can be successfully processed at 630°C with almost no impact on the performance and reliability of the bottom level. It is also highlighted that top level devices meet the P&NBTI reliability requirements. Finally an example of successful and robust 3D logic integration is proposed based on a 3D inverter combining a top-level PMOS with a bottom-level NMOS.
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Dates et versions

hal-02050384 , version 1 (27-02-2019)

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A. Tsiara, X. Garros, L. Brunet, P. Batude, C. Fenouillet-Beranger, et al.. Performance and Reliability of a Fully Integrated 3D Sequential Technology. 2018 IEEE Symposium on VLSI Technology, Jun 2018, Honolulu, United States. pp.75-76, ⟨10.1109/VLSIT.2018.8510625⟩. ⟨hal-02050384⟩
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