Toward Gated-Diode-BIMOS for thin silicon ESD protection in advanced FD-SOI CMOS technologies - Archive ouverte HAL
Communication Dans Un Congrès Année : 2017

Toward Gated-Diode-BIMOS for thin silicon ESD protection in advanced FD-SOI CMOS technologies

Résumé

This paper presents a new device named the Gated Diode merged BIMOS (GDBIMOS) which is fabricated using the 28nm UTBB FD-SOI high-k metal gate CMOS technology. It is highly reconfigurable and topologically robust for ESD protection. The suitable ESD window is achieved thanks to doping adjustment and to different possible gate connections.
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Dates et versions

hal-02007065 , version 1 (05-02-2019)

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Citer

Louise de Conti, Thomas Bedecarrats, Maud Vinet, Sorin Cristoloveanu,, Philippe Galy. Toward Gated-Diode-BIMOS for thin silicon ESD protection in advanced FD-SOI CMOS technologies. 2017 IEEE International Conference on IC Design & Technology (ICICDT), May 2017, Austin, United States. pp.44-47, ⟨10.1109/ICICDT.2017.7993509⟩. ⟨hal-02007065⟩
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