Towards a unified approach for worst-case analysis of Tilera-like and KalRay-like NoC architectures - Archive ouverte HAL Accéder directement au contenu
Communication Dans Un Congrès Année : 2016

Towards a unified approach for worst-case analysis of Tilera-like and KalRay-like NoC architectures

Résumé

In this paper, we consider two Network-on-Chip (NoC) architectures used within commercially available many-core systems, namely Tilera TILE64 which implements flow regulation within routers and KalRay MPPA 256 which implements flow regulation in source nodes. The Worst-Case Traversal Time (WCTT) on the NoC has to be bounded for real-time applications, and buffers should never overflow. Different worst-case analysis approaches have been proposed for each of these NoC architectures. However, no general worst-case analysis supporting both NoC architectures exists in the literature and most approaches are specific to one of the studied NoC. In this paper, we propose to use Recursive Calculus (RC) method for Tilera and KalRay. Furthermore, we compare the performances on a preliminary case study, in terms of WCTT and required buffer capacity. It allows to quantify the trade-off between delays and buffer occupancy.
Fichier principal
Vignette du fichier
Ayed_21542.pdf (464.64 Ko) Télécharger le fichier
Origine : Fichiers produits par l'(les) auteur(s)
Loading...

Dates et versions

hal-02001640 , version 1 (31-01-2019)

Identifiants

Citer

Hamdi Ayed, Jérôme Ermont, Jean-Luc Scharbarg, Christian Fraboul. Towards a unified approach for worst-case analysis of Tilera-like and KalRay-like NoC architectures. IEEE World Conference on Factory Communication Systems (WFCS 2016), May 2016, Aveiro, Portugal. pp.1-4, ⟨10.1109/WFCS.2016.7496535⟩. ⟨hal-02001640⟩
52 Consultations
69 Téléchargements

Altmetric

Partager

Gmail Facebook X LinkedIn More