This paper presents the relevant aspects of the design of an ultra-low-power frequency synthesizer based on the combination of two feedback loops, a Phase-Locked Loop (PLL) acting together with a Delay-Locked Loop (DLL) to perform fine and coarse tuning of the desired output frequency, respectively. The objective of the circuit is to achieve a power consumption lower than 100 µA to generate a 2.5 GHz output frequency, improving the poor phase-noise of ring oscillators with the usage of the DLL circuit as an auxiliary feedback loop to cancel the phase noise and adjusting the VCO frequency through the body bias feature, available in the 28 nm FDSOI technology from STMicroelectronics.