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Article Dans Une Revue IEEE Electron Device Letters Année : 2018

A Simple Method for Estimation of Silicon Film Thickness in Tri-Gate Junctionless Transistors

Résumé

Junctionless transistors (JLTs) without PN-junctions near the source/drain are promising candidates for further development of CMOS technology. The Si thickness of tri-gate JLTs is crucial to understand their unique electrical properties related to bulk neutral and surface accumulation conduction. A simple method based on a unique operation mechanism is suggested for extraction of tsi from measurements on tri-gate JLTs. The method was successfully applied to fabricated tri-gate JLTs and the extracted tsi values were comparable with those of transmission electron microscopy. Furthermore, the validity of the method was confirmed by 2-D numerical simulation.
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Dates et versions

hal-01948046 , version 1 (07-12-2018)

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Dae-Young Jeon, So Jeong Park, Mireille Mouis, Sylvain Barraud, Gyu-Tae Kim, et al.. A Simple Method for Estimation of Silicon Film Thickness in Tri-Gate Junctionless Transistors. IEEE Electron Device Letters, 2018, 39 (9), pp.1282-1285. ⟨10.1109/LED.2018.2857623⟩. ⟨hal-01948046⟩
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