Analytical Modeling of Threshold Voltage and Interface Ideality Factor of Nanoscale Ultrathin Body and Buried Oxide SOI MOSFETs With Back Gate Control - Archive ouverte HAL Accéder directement au contenu
Article Dans Une Revue IEEE Transactions on Electron Devices Année : 2014

Analytical Modeling of Threshold Voltage and Interface Ideality Factor of Nanoscale Ultrathin Body and Buried Oxide SOI MOSFETs With Back Gate Control

Résumé

Simple analytical models for the front and back gate threshold voltages and ideality factors with back gate control of lightly doped short channel fully depleted silicon-on-insulator ultrathin body and buried oxide thickness MOSFETs have been developed based on the minimum value of the front and back surface potentials. The threshold voltage and ideality factor models of the front and back gates have been verified with numerical simulations in terms of the device geometry parameters and the applied bias voltages, as well as with experimental results for devices with channel length down to 17 nm. Good agreement between the model, simulation, and experimental results were obtained by calibrating the minimum carrier charge density adequate to achieve the turn-on condition.
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hal-01947604 , version 1 (07-12-2018)

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Nikolaos Fasarakis, Theano Karatsori, Dimitrios Tassis, Christoforos Theodorou, François Andrieu, et al.. Analytical Modeling of Threshold Voltage and Interface Ideality Factor of Nanoscale Ultrathin Body and Buried Oxide SOI MOSFETs With Back Gate Control. IEEE Transactions on Electron Devices, 2014, 61 (4), pp.969-975. ⟨10.1109/TED.2014.2306015⟩. ⟨hal-01947604⟩
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