A path analysis based partitioning for time constrained embedded systems
Résumé
The HW/SW partitioning problem addressed in this paper is one of the key steps in the co-design flow of heterogeneous embedded systems. Generally the aim is to provide solutions that respect timing constraints and minimize an objective function such as the total area and/or the power consumption. Minimizing the hardware area conflicts with reducing execution time. Therefore, we introduce an heuristic for synthesizing heterogeneous systems that uses a global metric to guide the mapping of tasks according to the reusability of components and the time margin induced by timing constraints.
Mots clés
co-design flow
heterogeneous embedded systems
time margin
mapping
Embedded system
timing constraints
Signal processing algorithms
Energy consumption
Application specific integrated circuits
Real time systems
Silicon
Application software
Timing
Hardware
Time factors
HW/SW partitioning
time constrained embedded systems
partitioning
software engineering
path analysis
high level synthesis
logic partitioning
real-time systems