Spin transfer torque magnetic random-access memory: Towards sub-10 nm devices - Archive ouverte HAL
Communication Dans Un Congrès Année : 2018

Spin transfer torque magnetic random-access memory: Towards sub-10 nm devices

Résumé

Magnetic Random-Access Memory (MRAM) is a non-volatile class of solid-state storage device where the information is stored in the magnetic state of a ferromagnetic layer. Microelectronic industry has recently shown a strong interest for MRAM as they are very promising for embedded RAM applications and particularly embedded FLASH replacement. The main building bloc of an MRAM is a trilayer FM1/I/FM2 (Fig. 1.a) named magnetic tunnel junction (MTJ) , where FM1(2) refer to ferromagnetic layers and I to a thin insulating tunnel barrier (~ 1.2 nm). Nowadays researches are mainly focused on perpendicularly (p) magnetized tunnel junctions written by spin transfer torque (STT) , where the perpendicular axis is defined by the growth direction. FM1 is called the reference layer, its magnetization is pinned in one specific direction (for example, the up direction). FM2 is called the storage layer or free layer, its magnetization is free to be moved between its two stable states (up and down). The resistance of the stack depends on the relative orientation of the two magnetizations. The parallel (P) state (up/up) is a low resistance state while the antiparallel (AP) state (up/down) is a high resistance state, thus respectively coding the "0" and "1" of the binary logic. The tunneling magnetoresistance (TMR) is defined by the ratio =. The P and AP states are separated by an energy barrier Eb, used to define the thermal stability of the memory ∆= E /k T with kBT the thermal energy (Fig. 1.b). For practical applications, one aims for ∆ values from 60 to 100.
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Dates et versions

hal-01934505 , version 1 (26-11-2018)

Identifiants

Citer

N. Perrissin, S. Lequeux, N. Strelkov, L. Vila, L Buda-Prejbeanu, et al.. Spin transfer torque magnetic random-access memory: Towards sub-10 nm devices. 2018 International Conference on IC Design & Technology (ICICDT 2018), Jun 2018, Otrante, Italy. ⟨10.1109/ICICDT.2018.8399772⟩. ⟨hal-01934505⟩
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