Dopant implantation, followed by spike annealing is one of the main focus areas in the simulation of silicon processing due to its ability to form highly-activated ultra-shallow junctions. Coupled with the growing interest in the use of silicon-on-insulator (SOI) wafers, modelling and simulation of the influence of SOI structure on damage evolution and ultra-shallow junction formation on one hand, and on electrical MOSFET device characteristics on the other hand, are required. In this work, physically-based models of dopant implantation and diffusion, including amorphization, defect interactions and evolution, as well as dopant-defect interactions in both bulk silicon and SOI are integrated within a unique simulation tool to model the different physical mechanisms involved in the process of ultra-shallow junction formation. The application to 65 nm SOI MOSFET devices demonstrated the strong impact of the process simulation models on the simulated electrical device characteristics, in particular for both defect evolution and defect dopant interaction with the additional silicon/buried oxide (Si/BOX) interface. Simulation results of the threshold voltage (V th) and the variation of the on-and off-state currents of the explored structures are in good agreement with experimental data and can provide important insight for optimizing the process in both bulk silicon and SOI technologies.