Sub-15nm gate-all-around field effect transistors on vertical silicon nanowires - Archive ouverte HAL
Article Dans Une Revue Solid-State Electronics Année : 2017

Sub-15nm gate-all-around field effect transistors on vertical silicon nanowires

Résumé

A vertical MOS architecture implemented on Si nanowire (NW) array with a scaled Gate-All-Around (14 nm) and symmetrical diffusive S/D contacts is presented with noteworthy demonstrations in both processing (layer engineering at nanoscale), and in electrical properties (high electrostatic control, low defect level, multi-Vt platform). Furthermore, the versatility and reliability of this technology is evidenced with a CMOS inverter, providing bright perspectives for ultimate scaling.
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Dates et versions

hal-01898405 , version 1 (18-10-2018)

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Guilhem Larrieu, Youssouf Guerfi, X.L. Han, N. Clément. Sub-15nm gate-all-around field effect transistors on vertical silicon nanowires. Solid-State Electronics, 2017, 130, pp.9 - 14. ⟨10.1016/j.sse.2016.12.008⟩. ⟨hal-01898405⟩
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