Proposal of a new ultra low leakage 10T sub threshold SRAM bitcell
Résumé
The tendency for low energy consumption in systems-on-chip results in a need for memories operating in the near- and sub-threshold regions. This paper gives a comparative study of Static Random Access Memory (SRAM) bitcells working under Ultra-Low Voltage in 32nm CMOS. A new 10T SRAM bitcell is then proposed and features low leakage current. It is capable of operation under ULV (~300mV) and allows bit-interleaving technique that is critical to cope with multiple bit soft-errors for reducing dynamic and static power consumption compared to state-of-the-art bitcells.