Proposal of a new ultra low leakage 10T sub threshold SRAM bitcell - Archive ouverte HAL
Communication Dans Un Congrès Année : 2012

Proposal of a new ultra low leakage 10T sub threshold SRAM bitcell

Résumé

The tendency for low energy consumption in systems-on-chip results in a need for memories operating in the near- and sub-threshold regions. This paper gives a comparative study of Static Random Access Memory (SRAM) bitcells working under Ultra-Low Voltage in 32nm CMOS. A new 10T SRAM bitcell is then proposed and features low leakage current. It is capable of operation under ULV (~300mV) and allows bit-interleaving technique that is critical to cope with multiple bit soft-errors for reducing dynamic and static power consumption compared to state-of-the-art bitcells.
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Dates et versions

hal-01865458 , version 1 (31-08-2018)

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Anis Feki, Bruno Allard, David Turgis, Jean-Christophe Lafont, Lorenzo Ciampolini. Proposal of a new ultra low leakage 10T sub threshold SRAM bitcell. ISOCC, Nov 2012, Jeju Island, South Korea. ⟨10.1109/ISOCC.2012.6406898⟩. ⟨hal-01865458⟩
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