This paper presents a method for decoding high minimal distances (dmin) short codes termed Cortex codes. These codes are systematic block codes of rate 1/2 and can have higher dmin than turbo codes. Despite this characteristic, these codes were impossible to decode with good performance. This is due to the fact that to reach high dmin, several encoding stages are connected through interleavers. This generates a large number of hidden variables and complexifies the scheduling and the initialization. However, the structure of the encoder is well suited for analog decoding. A proof-of-concept Cortex decoder for the (8,4,4) Hamming code has been implemented in subthreshold 0.25-µm CMOS. It outperforms an equivalent LDPC-like decoder by 1dB at BER=10E-5 while being 44 percent smaller and consuming 28 percent less energy per decoded bit