The most widely used embedded memory technology, SRAM (Static Random Access Memory), is heading towards scaling problems in advanced technology nodes, due to the leakage currents caused by the quantum tunneling effect. As an alternative, STT-MRAM (Spin Transfer Torque Magnetic Random Access Memory) technology shows comparable performances in terms of speed and power consumption, and much better ones in terms of density and leakage. Moreover, MRAM brings up new paradigms in system design thanks to its inherent non-volatility, which allows the definition of new instant on/off policies and leakage current optimization. Based on our compact model, we have developed a fully characterized SoC (System on Chip) from the basis cell up to the system architecture in a 40nm LP hybrid CMOS/magnetic process. Through simulations, we have firstly demonstrated that STT-MRAM is a candidate for the memory part of embedded systems and have secondly implemented a check-pointing methodology based on the regular interrupt routines of a processor to enable a fast power on and off functionality. Using a synthetic benchmark developed in high level programming languages intended to be representative of integer system performance, our method shows that having MRAM instead of SRAM in an embedded design brings up important energy savings. The influence of the check-pointing routine on the power consumption is finally evaluated with regards to various shutdown and restart behaviors.