Analog slice turbo decoding
Résumé
This paper presents the design of an analog turbo decoder for the DVB-RCS standard. It uses a slice architecture which enhances the design in terms of simplicity, robustness, testability and reusability. Transistor-level simulations show po- tential throughput up to 1.2Gb/s for a 2.8mW power consumption per information bit and per state in a 0.25μm BiCMOS process.
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