Analogue decoding of duo-binary codes
Résumé
This paper presents the design of an analogue decoder for convolutional duo-binary codes targeting an industrial application for the DVB-RCS standard. The decoder implements the MAP algorithm and is designed for a 0.25um BiCMOS SiGe process. Simulations at transistor level validate the decoding of frames made up of 24 duo-binary symbols. Its power consumption per information bit and per state is simulated at 1.4mW which is comparable to what was obtained in a previous work for simpler and shorter codes. The decoding speed is estimated at 600Mbit/s. This elementary decoder is then used in a turbo scheme in order to implement the complete DVB-RCS decoder. Behavioural simulations show that the analogue MAP decoding enhances the error correcting performance by 0.1dB (at a BER of 104) compared to its optimal digital equivalent.
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