The Fully-Depleted Silicon-on-Insulator (FD-SOI) technology for advanced CMOS devices is based on SOI substrates formed by an ultra-thin Si or SiGe film on a thick insulator. A reduction of parasitic resistances of such CMOS components is obtained with the Raised Source and Drain (RSD) technology. In this work we show that modifying the Siconi TM plasma-based etching process widely used in microelectronic and/or combining it to wet-etching methods allows to improve the principal steps of fabrication of RSD FD-SOI CMOS devices. More precisely, using sampling areas on 300 mm wafers that simulate the principal stages of FD-SOI building, (i) we show that a modified SiCoNi process may be used to increase the etching selectivity necessary to dissolve the oxide layer while maintaining a low-k spacer of high quality, (ii) we propose a combination of optimized SiCoNi-dry and wet etching that reduces the post-etching roughness and the contamination level of the channel surface before the subsequent epitaxy.