Scalability of split-gate charge trap memories down to 20nm for low-power embedded memories
Résumé
In this work, split-gate charge trap memories with electrical gate length down to 20nm are presented for the 1 st time. Silicon nanocristals (Si-ncs), or silicon nitride (Si 3 N 4) and hybrid Si-nc/SiN based split-gate memories, with SiO 2 or Al 2 O 3 control dielectrics, are compared in terms of program erase and retention. Then, the scalability of split-gate charge trap memories is studied, investigating the impact of gate length reduction on the memory window, retention and consumption. The results are analyzed by means of TCAD simulations.
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