Performance degradation induced by fringing field-induced barrier lowering and parasitic charge in double-gate metal-oxide-semiconductor field-effect transistors with high-kappa dielectrics - Archive ouverte HAL Accéder directement au contenu
Article Dans Une Revue Japanese Journal of Applied Physics Année : 2005

Performance degradation induced by fringing field-induced barrier lowering and parasitic charge in double-gate metal-oxide-semiconductor field-effect transistors with high-kappa dielectrics

Résumé

The electrical behavior of a decananometer double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) with high-permittivity (high-kappa) and stacked-gate dielectrics has been investigated using two-dimensional (2D) quantum numerical simulation. We show that in spite of a quasi-ideal control of the channel by the gates in the double-gate structure, the device performances can be significantly degraded when using high-K dielectrics due to two important electrostatic limitations of high-kappa materials: i) the fringing field-induced barrier lowering effect (FIBL) and ii) the presence of discrete fixed charges in the gate stack. The FIBL compromises the performance of short-channel devices when simultaneously increasing the dielectric constant and its physical thickness, whereas the charges trapped in the high-kappa layer induce 2D potential fluctuations in the structure and degrades the subthreshold behaviour of the drain current.
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Dates et versions

hal-01759458 , version 1 (05-04-2018)

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Jean-Luc Autran, Daniela Munteanu, M Houssa, K Castellani-Coulie, A Said. Performance degradation induced by fringing field-induced barrier lowering and parasitic charge in double-gate metal-oxide-semiconductor field-effect transistors with high-kappa dielectrics. Japanese Journal of Applied Physics, 2005, 44 (12), pp.8362-8366. ⟨10.1143/JJAP.44.8362⟩. ⟨hal-01759458⟩
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