An analytical model of the threshold voltage for long channel double-gate metal-oxide-semiconductor field effect transistor is developed, applicable to both symmetric and asymmetric structures with thin films (< 10 nm) and high-permittivity gate dielectrics (with permittivities > 10). The model takes into account short-channel effects, carrier quantization and fringing-field induced barrier lowering induced by the high-permittivity gate layer. The model assumes a parabolic dependence of the potential with position in the silicon film at threshold, enabling the development of an analytical expression for the surface potential. Compared to previous models only derived for undoped films, the present approach considers both mobile charge and depleted charge terms in Poisson's equation. The model is fully validated by numerical simulation and is used to predict the impact of the fringing-induced barrier lowering on the threshold voltage of double-gate devices as a function of the gate stack composition and the device gate length. (c) 2005 Elsevier B.V. All rights reserved.