In this paper we present a detailed simulation analysis of the impact of geometrical (channel length, silicon film thickness and gate oxide thickness) and electrical (channel doping level and supply voltage) parameters on speed performance characteristics of double-gate metal-oxide-semiconductor field-effect transistor (MOSFET). Essential indicators of the speed performance characteristics, such as inverter delay, gate capacitances and ratio between on-state current (ION) and off-state current (I-OFF), are investigated as a function of the device architecture. The study provides important guidelines for optimizing the double-gate structure in order to obtain the best compromise between power consumption and switching speed. The simulation results show that a single reduction in gate length (without modifying other device parameters) decreases the complementary MOS (CMOS) inverter delay, but strongly increases the power consumption. The reduction in channel length must be accompanied by the use of ultrathin and low doped silicon films in order to reduce the power consumption without increasing the inverter delay. [DOI: 10.1143/JJAP.47.3390]