Advanced structures with poly-Si gates, Si3N4 spacers, and shallow trench isolation (STI) areas were used for elaborating the selective growth of Si1−yCy films into recessed source and drain (S/D). Selective Si1−yCy films were grown by repeated cycles consisting of two distinct steps: a non-selective CVD growth of Si1−yCy layers, and a chemical vapor etching with hydrochloric gas. This cyclic deposition/etching process has been experimented at 600 °C with a methylsilane/(methylsilane+trisilane+hydrogen) mass flow ratio (SiCH6 MFR) equal to 2.8×10−4 used for Si0.99C0.01 film deposition. Regarding etching step, a pure HCl gas/(hydrogen) mass flow ratio (HCl MFR) was about 4.3×10−1. We should note that the poly-crystalline Si1−yCy layers are etched more rapidly than the mono-crystalline layers. The etching rate ratio between poly and mono areas induces the capability, by cyclic process, to remove the deposited poly-crystalline Si1−yCy layers on the dielectric areas (STI, spacers) selectively versus the recessed mono-crystalline Si1−yCy layers. A global time process, of about 3 h, resulted in 50 nm thick Si0.99C0.01 films selectively grown into recessed S/D. The new TEM technique of dark-field holography was used to determine a mapping of the strain at transistor level (within Si channel among S/D). The tensile stress of about 0.2 GPa has been measured within Si channel (300 nm length) among recessed Si0.985C0.015 films.