Critical sensitivity of flash gate dimension spread on electrical performances for advanced embedded memory
Résumé
In this paper a correlation between specific inline and electrical parameters has been deeply investigated. This study shows the impact of the flash gate intra-die and intra-wafer spread on the memory performances. A process recipe optimization has been evaluated to recover the effects of these variations. This optimization allows us to reduce the written threshold voltage intra-wafer spread by fifty percent.
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Critical sensitivity of Flash gate dimension spread on electrical performances for advanced embedded memory - final.pdf (619.09 Ko)
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