The incorporation of compressive strained Ge/tensile strained Si bi-layers in the active regions of MOSFETs is a promising route for creating ultimate Si-based devices due to the considerable increase of the mobility of spatially confined holes/electrons. The main challenge in device application is to be able to control and manipulate strain within such thin layers. This paper reports on quantitative measurements of strain in a structure consisting of a 8 nm Ge/5 nm Si heterostructure grown by chemical vapour deposition on top of a relaxed Si0.5Ge0.5 buffer layer. Geometric phase analysis of high resolution TEM images is used to measure the strain within Ge and Si layers. The in-plane stress within each layer is deduced. Experimental results are compared with the predictions of elasticity theory and discussed in terms of effect of defect formation.