This paper presents an in-depth analysis of the impact of body-biasing, supply voltage, and temperature on the detection of resistive short defects in FDSOI technology. Three types of short defects are considered for our investigation, namely resistive short to ground terminal, resistive short to power supply terminal (VDD), and intergate resistive bridging defect. The two implementation options offered by the technology, i.e., low VT (LVT) and regular VT (RVT) devices are also studied. Defect detectability is evaluated in the context of logic test using the concept of critical resistance. The optimal body-biasing, supply voltage, and temperature settings to achieve the maximum defect coverage are determined through HSPICE simulations using a didactic circuit implemented with 28-nm UTBB FDSOI gate library. An analytical analysis is also proposed based on the on-resistance model of P and N networks, which permits to evaluate the value of the critical resistance without performing fault simulations. In addition, this paper quantifies the individual as well as the combined improvements in detection brought by body-biasing, supply voltage, and temperature settings for the different defect types and different implementations.