Computing Routes and Delay Bounds for the Network-on-Chip of the Kalray MPPA2 Processor - Archive ouverte HAL Access content directly
Conference Papers Year : 2018

Computing Routes and Delay Bounds for the Network-on-Chip of the Kalray MPPA2 Processor

Benoît Dupont de Dinechin
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Amaury Graillat
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Lionel Havet
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Abstract

The Kalray MPPA2 manycore processor implements a clustered architecture, where clusters of cores share a local memory, and communicate through a RDMA-capable network-on-chip (NoC). This NoC has been designed to allow guaranteed delays by the adequate configuration of traffic limiters at ingress and the choice of routing. We first present the challenges related to the routing of concurrent flows and a strategy that solves it. Routing challenges include deadlock-free routing, which is always an issue on wormhole switching networks, fairness of resource allocation between flows, and ensuring the feed-forward property required by deterministic network calculus (DNC). Second, we present a linear formulation based on DNC for computing end-to-end delay bounds of concurrent feed-forward flows on the MPPA2 NoC. Finally, we compare this linear formulation to a classic formulation originally designed for the AFDX avionics networks.
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Dates and versions

hal-01707911 , version 1 (13-02-2018)

Identifiers

  • HAL Id : hal-01707911 , version 1

Cite

Marc Boyer, Benoît Dupont de Dinechin, Amaury Graillat, Lionel Havet. Computing Routes and Delay Bounds for the Network-on-Chip of the Kalray MPPA2 Processor. ERTS 2018 - 9th European Congress on Embedded Real Time Software and Systems, Jan 2018, Toulouse, France. ⟨hal-01707911⟩
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