Exploiting at best every bit of memory on chip is a must for finding the best trade-off between cost and performance when designing Many-Core MPSoCs. In this paper, we propose a new memory hierarchy organization that maximizes the usage of the available memory at each cache level while avoiding data redundancy. We also aim to reduce data access time by avoiding data migration. Our scheme is based on Non-Uniform Cache Architectures (NUCA), and makes use of a novel NoC multicast messaging support. It requires to logically partition the network into imagined layers in which each layer is bound to one of the cache levels. We assess the efficiency of our proposal by evaluating performance metrics, using the Gem5 simulator and the Splash2 benchmark suite. Our results show an improvement of 24% in L2 miss rate over baseline S_NUCA organization and more than 25% in average network latency. We report a maximum improvement of 40% in execution time. Also, we show that our approach ou tperforms R_NUCA.