Doing early design space exploration for manycore architectures is a challenge, all the more when the focus is on complex coherence protocols. Implementing such protocols in realistic simulation models is costly both in modelling effort and execution time. We propose a trace-driven method to accurately compare cache coherence protocols while keeping cache modelling at a high level of abstraction. We show what kind of design space exploration can be performed on an existing sharing set implementation proposal, the linked list sharing set management. By doing so, we demonstrate that our approach, while being still fairly accurate, is much easier to develop and much faster to execute than state of the art low level simulators.