Multiple FPGA-based prototyping plays an important role in the design and verification process due to their low cost and high execution speed. However, there is a need to optimize the configuration flow of this multiple FPGA-based prototyping. In this paper, we address the partitioning of large designs and propose a debugging methodology for these partitioned designs using Signal Tap II embedded logic analyzer by Quartus tool of Altera. Usually SignalTap II tool is used to debug design implemented on single FPGA and this logic analyzer debugs FPGA device by probing the states of internal signals without using external debug equipment. However, we use SignalTap II logic analyzer for large designs on multiple FPGAs and we facilitate the debugging methodology for thousands of signals under consideration. We propose the debugging of large designs after partitioning by developing the techniques to trace the required signals under test through multiple FPGAs without using FPGA internal memory. We have generated various large benchmarks as well and tested them for multiple FPGA-based prototyping.