Design Considerations of a CMOS Envelope Detector for Low Power Wireless Receiver Applications - Archive ouverte HAL
Communication Dans Un Congrès Année : 2017

Design Considerations of a CMOS Envelope Detector for Low Power Wireless Receiver Applications

Résumé

Previous studies have shown that a transistor's transconductance-to-drain-current ratio is useful for optimizing analog circuits. In this paper, we derive an expression that captures the second order distortion generated at the output of an envelope detector. We use the derived expression, along with the nonlinear Taylor series coefficients to design a 3 μA envelope detector in 0.13 μm CMOS process.
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Dates et versions

hal-01657109 , version 1 (13-10-2022)

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Jack Ou, Pietro Maris Ferreira. Design Considerations of a CMOS Envelope Detector for Low Power Wireless Receiver Applications. New Circuits and Systems Conference (NEWCAS), 2017 15th IEEE International, Jun 2017, Strasbourg, France. ⟨10.1109/newcas.2017.8010148⟩. ⟨hal-01657109⟩
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