Design Considerations of a CMOS Envelope Detector for Low Power Wireless Receiver Applications
Résumé
Previous studies have shown that a transistor's transconductance-to-drain-current ratio is useful for optimizing analog circuits. In this paper, we derive an expression that captures the second order distortion generated at the output of an envelope detector. We use the derived expression, along with the nonlinear Taylor series coefficients to design a 3 μA envelope detector in 0.13 μm CMOS process.
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Ou, Ferreira - 2017 - A CMOS Envelope Detector for Low Power Wireless Receiver Applications.pdf (374.31 Ko)
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