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Conference Papers Year : 2018

Supporting Runtime Reconfigurable VLIWs Cores Through Dynamic Binary Translation

Abstract

Single ISA-Heterogeneous multi-cores such as the ARM big.LITTLE have proven to be an attractive solution to explore different energy/performance trade-offs. Such architec-tures combine Out of Order cores with smaller in-order ones to offer different power/energy profiles. They however do not really exploit the characteristics of workloads (compute-intensive vs. control dominated). In this work, we propose to enrich these architectures with runtime configurable VLIW cores, which are very efficient at compute-intensive kernels. To preserve the single ISA programming model, we resort to Dynamic Binary Translation , and use this technique to enable dynamic code specialization for Runtime Reconfigurable VLIWs cores. Our proposed DBT framework targets the RISC-V ISA, for which both OoO and in-order implementations exist. Our experimental results show that our approach can lead to best-case performance and energy efficiency when compared against static VLIW configurations.
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Dates and versions

hal-01653110 , version 1 (01-12-2017)
hal-01653110 , version 2 (05-12-2017)

Identifiers

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Simon Rokicki, Erven Rohou, Steven Derrien. Supporting Runtime Reconfigurable VLIWs Cores Through Dynamic Binary Translation. DATE 2018 - IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition, Mar 2018, Dresden, Germany. pp.1009-1014, ⟨10.23919/DATE.2018.8342160⟩. ⟨hal-01653110v2⟩
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