This paper presents a PCI compliant three-state input/output pad that feature low power consumption, absence of passive elements and easy mapping an different target processes. Firstly, we quickly present a portable approach to layout using a process independent unit, named /spl lambda/, that allows to scale the design. Secondly, we introduce the PCI requirements, and outline the important constraints for CMOS pads design: minimum fan-out and maximum slew rate are incompatible using a simple buffer. Finally, we propose a schematic in the which driving power and slew rate are controlled independently. Compared to other possible designs that could include passive elements, this full transistor approach greatly simplifies technology migration and turns out to minimise power consumption. Transistors' size for output power and slew rate control are determined using a few spice simulations. PCI compliance has been obtained on two 0.8 /spl mu/m processes under 5 V, and two 0.5 /spl mu/m processes under 3.3 V with the same transistors size in /spl lambda/.