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Communication Dans Un Congrès Année : 2017

A 28GHz self-contained power amplifier for 5G applications in 28nm FD-SOI CMOS

Résumé

This paper presents a 28 GHz CMOS balanced Power Amplifier (PA) with integrated quadrature hybrid couplers to achieve robust load insensitivity for 5G phased array applications. The proposed balanced PA achieves a saturated output power (Psat) of 18.7dBm and a maximum Power Added Efficiency (PAEmax) of 12.4% with 17.5dB gain. It consumes 154mW and occupies 0.66mm² of die area. Each power cell is based on class-AB Segmented Biased Push-Pull (SBPP) topology to improve both the AM-AM and AM-PM conversion. The circuit is implemented in 28nm UTBB FD-SOI CMOS technology taking, advantage of the back gate for threshold voltage adjustment.

Domaines

Electronique
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Dates et versions

hal-01618222 , version 1 (17-10-2017)

Identifiants

  • HAL Id : hal-01618222 , version 1

Citer

Boris Moret, Vincent Knopik, Eric Kerherve. A 28GHz self-contained power amplifier for 5G applications in 28nm FD-SOI CMOS. 2017 IEEE 8th Latin American Symposium on Circuits Systems (LASCAS), Feb 2017, San Carlos de bariloche, Argentina. ⟨hal-01618222⟩
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