In this paper, we present some pattern recognition algorithms based on the Gabor filtering. We then select an algorithm showing best performance and readiness for a hardware implementation. We focus this paper on the problem of algorithm/architecture adequation. We present a design methodology considering algorithm study and refining, hardware resources, data widths and final cost of the system implementing the considered algorithm. The whole system is simulated using a hardware/software cosimulation tool and will be implemented following a macro-block generator design strategy. This is of great importance as to the emergence of the new techniques of IP block design. The design will thus be portable, upgradable and parametrizable.