This paper presents a new functional abstraction tool for CMOS VLSI. The tool uses a procedure called circuit disassembly in order to extract an oriented gate netlist from a transistor netlist. Logic equations are then generated for these extracted gates in order to produce a VHDL data-flow description for a circuit. This tool combines an advanced functional analysis technique with subgraph isomorphism algorithms in order to handle the widest possible number of circuit styles with a minimum of user intervention.