This paper details the design and implementation of a centralized bus arbiter implementing programmable fixed priorities arbitration. The arbiter also handles default master grant to the master with highest priority. The arbitration algorithm is computed using a tree of specialized comparators to fully exploit hardware parallelism. The design is implemented as a generic VHDL model whose parameter is the number of masters. After synthesis and place & route, a 16 masters arbiter has a critical path delay of 7.5 ns in 0.5 /spl mu/m technology.