This paper deals with the implementation of the GSM EFR vocoder on a configurable DSP processor. We first present the highly configurable and modular architecture used in the model of our DSP core. Next, a quantitative analysis of the EFR algorithm regarding Instruction-Level Parallelism and Algorithm/Architecture Adequation is performed. This leads to define a cost-effective and powerful architecture with special features enabling an optimized implementation of the vocoder. The results obtained are shown and compared to those of state-of-art DSP Processors.