In this paper, the main sources of nonlinearity in current-mode continuous-time /spl Sigma//spl Delta/ modulators are analyzed. The first integrator gain of the current-mode integrator is optimized to improve the linearity of the /spl Sigma//spl Delta/ modulator. It is shown that by properly choosing the gain of the first integrator, harmonic distortion can be significantly reduced. A systematic design method for continuous-time /spl Sigma//spl Delta/ modulators is presented. This method has been used to design two third order continuous-time /spl Sigma//spl Delta/ modulators using 0.6 /spl mu/m and 0.18 /spl mu/m CMOS processes. Operating at a sampling frequency of 25.6 MHz, these modulators achieve 80 dB of SNDR for a 100 kHz input signal bandwidth.