To certify the correctness of a design, in deep submicron technologies, the verification process has to cover some new issues. The noise introduced on signals through the crosstalk coupling is one of these emerging problems. In this paper, we expose a first model to evaluate the peak value of the noise injected on a signal during the transition of its neighboring signals. Then, analysing the error introduced by each step of simplification in this model, we propose a new MOS transistor model.