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Communication Dans Un Congrès Année : 2003

SPIN: a Scalable, Packet Switched, On-Chip Micro-network

Résumé

This paper presents the SPIN micro-network that is a generic, scalable interconnect architecture for system on chip. The SPIN architecture relies on packet switching and point-to-point bi-directional links between the routers implementing the micro-network. SPIN gives the system designer the simple view of a single shared address space and provides a variable number of VCI compliant communication interfaces for both initiators (masters) and targets (slaves). Performance comparisons between a classical PI-bus based interconnect and the SPIN micro-network are analyzed.

Dates et versions

hal-01529871 , version 1 (31-05-2017)

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Adrijean Andriahantenaina, Hervé Charlery, Alain Greiner, Laurent Mortiez, Cesar Albenes Zeferino. SPIN: a Scalable, Packet Switched, On-Chip Micro-network. Design Automation and Test in Europe Conference (DATE'2003) Embedded Software Forum, Mar 2003, Munich, Germany. pp.70-73, ⟨10.1109/DATE.2003.1253808⟩. ⟨hal-01529871⟩
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