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Communication Dans Un Congrès Année : 2016

Delay partitioning helps reducing variability in 3DVLSI

Résumé

3DVLSI is an emerging more than Moore technology. In this paper, we propose 3D design methodologies dealing with process variability. Using SPICE models and Monte Carlo simulations we show a delay partioning method for stacked circuits to reduce frequency dispersion by 30%. We also compare how the process correlation between tiers influences the design corners.
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Dates et versions

hal-01524088 , version 1 (17-05-2017)

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Paternité - Pas d'utilisation commerciale

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Citer

A. Ayres, O. Rozeau, B. Borot, Laurent Fesquet, M. Vinet. Delay partitioning helps reducing variability in 3DVLSI. 42nd European Solid-State Circuits Conference (ESSCIRC'16), Sep 2016, Lausanne, Switzerland. pp.75-78, ⟨10.1109/ESSCIRC.2016.7598246⟩. ⟨hal-01524088⟩
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