Architectural exploration and application development for digital System On Chip (SoC) need more and more performance from the simulator. Today, the standard design flow use a unifed modeling language and only one simulator for every development step. SystemC based simulators are efficient to validate hardware speclfications but its performances are not good enough to write and debug embedded softwares. Using some specialized simulators increase the effectiveness of a particular step. So, we specialize the simulator to become more suitable for targeted steps. In this paper, we describe an approach to accelerate simulation performances by focusing on the cycle accurate simulation level.