Communication Dans Un Congrès Année : 2017

Tunnel FET Based Refresh-Free-DRAM

Résumé

A refresh free and scalable ultimate DRAM (uDRAM) bitcell and architecture is proposed for embedded application. uDRAM 1T1C bitcell is designed using access Tunnel FETs. Proposed design is able to store the data statically during retention eliminating the need for refresh. This is achieved using negative differential resistance property of TFETs and storage capacitor leakage. uDRAM allows scaling of storage capacitor by 87% and 80% in comparison to DDR and eDRAMs, respectively. Bitcell area of 0.0275$\mu$m$^2$ is achieved in 28nm FDSOI-CMOS and is scalable further with technology shrink. Estimated throughput gain is 3.8% to 18% in comparison to CMOS DRAMs by refresh removal.

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Dates et versions

hal-01515827 , version 1 (28-04-2017)

Identifiants

  • HAL Id : hal-01515827 , version 1

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Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel. Tunnel FET Based Refresh-Free-DRAM. Design, Automation, and Test in Europe, Mar 2017, Lausanne, Switzerland. ⟨hal-01515827⟩
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