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Conference Papers Year : 2016

A survey of NoC evaluation platforms on FPGAs

Abstract

Networks-on-chip (NoCs) have become a de facto communication standard for many core systems-on-chip (SoCs). A NoC has large design space composed of several parameters such as routing algorithm, task mapping, flow control method, among others. SoC designers deeply rely on automatic evaluation tools in order to deal with the complexity of NoC design. An important class of NoCs evaluation tools are the platforms based on FPGAs, which improve the evaluation time and precision when compared to other solutions like software simulators and analytical models. In this paper, we survey propositions of FPGA tools for NoC evaluation by using a layered model, which covers aspects like network architecture, traffic generation and interface to the host PC
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Dates and versions

hal-01499096 , version 1 (30-03-2017)

Identifiers

  • HAL Id : hal-01499096 , version 1

Cite

Otávio Alcântara de Lima Jr, Weslley N. Costa, Virginie Fresse, Frédéric Rousseau. A survey of NoC evaluation platforms on FPGAs. The 2016 International Conference on Field-Programmable Technology, Dec 2016, Xian, China. ⟨hal-01499096⟩
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