With increased complexity and shorter development cycle of hardware, designers cannot afford to redesign similar subcomponents. They have to focus on the global design, and must extract a validated netlist from the specification of some classic component, thus insuring good performance and adaptation to their needs. In this paper, we present the design methodology for a FIR filter netlist generator, the FIR filter being one of the most frequently used device in digital signal processing. Starting from mathematical equation and specification parameters, we include arithmetic knowledge in the generator, allowing architecture choices based on filter properties and realistic parameters values. We also provide a rounding option and a validation framework.