Prediction of failures induced during system level ESD stress is mainly related to the transient waveforms at chip level. To investigate hard and soft failures a precise modeling of the system is required. On-chip protection models can be obtained using quasi-static measurements. Even if such models can achieve good ESD simulations the impact of the external elements are more important. Paper deals with non-linear behaviors of the external elements related to the on-chip protections. Characterization techniques and models are presented, based on two types of capacitances, two different values, placed in parallel to on-chip protections. The paper shows the important variations of X7R capacitances during stresses that change the waveforms at the input of the chip. In measurements different behaviors are observed and reproduced by simulation. The methodology to build model and simulation will be presented.